The present invention relates to an accurate delay circuit for use in reading data from a disk drive. More particularly, the present invention relates to an accurate delay circuit which is used to anticipate a phase comparison and initiate a zero phase restart.
In the art of data recording, data is stored in a disk drive system by positioning a read/write transducer head proximate a rotating magnetic disk. A write signal is applied to the read/write head causing the head to emit a transient magnetic field, which creates a series of magnetic polarizations on the disk surface. The write signal is created by synchronizing the data to be written with a write clock signal. Typically, the write clock signal itself is not written to the disk surface.
When reading data from the disk, the read/write head passes over the magnetic polarizations. This induces a transducer signal in the read/write head. The transducer signal is processed to form a read signal. Because the write clock signal which originally synchronized the data is not itself written to the disk, a read clock signal must be recreated to frame the data embedded in the read signal. The read clock signal must compensate for variations in the rate at which data is read from the disk. These variations are typically caused by imperfections in the servo mechanism that rotates the disk, and by vibrations.
It is known in the art to utilize a phase locked loop to create a read clock signal which can frame the data embedded in the read signal. A typical phase locked loop is comprised of a voltage controlled oscillator (VCO), a phase detector, a charge pump and a loop filter. The VCO receives an input voltage and produces an output signal having a frequency which varies with the magnitude of the input voltage. A read clock signal is derived from the VCO output signal (typically by applying the VCO output signal to a frequency divider). The phase detector compares the phase of the read clock signal with the phase of the read signal.
If the phase of the read clock signal lags the phase of the read signal, the phase detector will issue a pump-up signal to the charge pump. The pump-up signal raises the voltage delivered to the VCO input, thereby raising the frequency of the VCO output signal and the read clock signal. If the phase of the VCO output signal leads the phase of the read signal, then the phase detector will issue a pump-down signal to the charge pump. The pump-down signal lowers the voltage supplied to the VCO, thereby lowering the frequency of the VCO output signal and the read clock signal. Accordingly, the read clock signal will eventually lock on to the read signal.
By itself, the phase locked loop described above will not create a read clock signal suitable for framing data embedded in a read signal. The read signal will not contain a transition every clock period, and therefore, the phase detector cannot determine when to perform a phase comparison. If the phase detector attempted to perform a phase comparison when it detected a transition in the read signal, it could perform a proper comparison only if the phase of the read signal led the phase of the read clock signal. When the phase of the read signal lags the phase of the read clock signal, the phase detector will miss the phase comparison because the transition in the read clock signal will have already occurred when the phase detector is signaled to perform a phase comparison. This would cause the phase detector to perform a phase comparison on the next transition of the read clock signal, and the phase detector would incorrectly determine that the phase of the read clock signal lagged the phase of the read signal. Accordingly, the phase locked loop described above must be provided with a mechanism which performs a phase comparison on the appropriate transition of the read clock signal whenever a transition occurs in the read signal.
It is known in the art to provide the phase locked loop described above with a delay circuit which delays the read signal by a time interval related to the expected rate at which data is read from the disk. The delay circuit allows every transition in the read signal from one voltage level to another voltage level to trigger a phase comparison. When a transition is present in the read signal, the transition is detected before being delayed by the delay circuit. Based on this initial detection, the phase detector is signaled to perform a phase comparison. The phase comparison is then performed on the delayed read signal, thereby allowing the phase detector to perform a phase comparison regardless of whether the phase of the read clock signal leads or lags the phase of the read signal.
Typical delay circuits include RC circuits and circuits comprised of a string of inverters. An RC delay circuit typically has a delay based on a time interval required for a capacitance to charge from one voltage level to another voltage level. A delay circuit based on a string of inverters has a delay interval equal to the propagation delay of each inverter multiplied by the number of inverters.
The accuracy of the delay circuit is critical. If the delay is significantly in error, the phase detector will compare a transition in the delayed read signal with an incorrect transition in the read clock signal. Designing an accurate delay circuit has proven to be challenging, particularly in integrated circuit environments where component values typically vary by 20 percent due to fabrication variations.
With the advent of zone density recording, not only must the delay circuit be accurate, it must also be variable. In a typical disk drive not having zone density recording, the disk surface is divided into tracks and sectors. Tracks are defined as concentric rings of the disk surface. Sectors are defined by equally dividing tracks by lines extending radially outward from the center of the disk surface. Each sector traverses an arc equal to arcs traversed by the other sectors. Accordingly, sectors on the edge of the disk surface contain more recording media than sectors close to the center of the disk surface. Because the rate at which data is written to the disk surface remains constant, recording media on the outer edge of the disk surface is not used as efficiently as recording media near the center of the disk surface.
In zone density recording, the rate at which data is written to the disk surface varies with the radial distance at which data is written. Data written near the center of the disk surface is written at a slower rate than data written near the outer edge of the disk surface, thereby utilizing the outer tracks of the disk surface more efficiently. Unfortunately, zone density complicates the design of read/write circuitry, including the delay circuit.
An accurate delay circuit for use in integrated circuit environments was disclosed by Lofgren et al in U.S. Pat. No. 4,922,141. The delay circuit disclosed by Lofgren et al is comprised of a crystal oscillator, a phase detector and first and second variable delay circuits. A reference frequency signal provided by the crystal oscillator is applied to the first variable delay circuit. The phase detector compares the phase of the delayed signal from the first variable delay circuit with the phase of the reference frequency signal. An error signal generated by the phase detector is applied to the first variable delay circuit, thereby forming a phase locked loop. The phase detector causes the two signals to become in-phase by varying the error signal, which varies the delay of the first delay circuit until the delay interval equals one oscillation period of the reference signal.
The error signal is also applied to the second delay circuit. Since both delay circuits are located on the same integrated circuit, deviations in their respective component values will track. Therefore, the second delay is provided with a delay having an accurate relationship to the delay of the first delay circuit, which is equal to the oscillation period of the oscillator.